C_UART
Universal Asynchronous Receiver/Transmitter
Synthesizable Core
Function Description
The C_UART core is a generic universal asynchronous receiver/transmitter (UART) and can
be used to implement a peripheral data communication device. The designer can program the
core with an 8-bit CPU.
Features such as character length, parity, and programmable start/stop bits can easily
be added into the core. Contact CAST for additional information.
Features
- 8 bit characters
- TxC / RxC (16 times the desired output baud rate)
- 1 start bit / 1 stop bit
- Polling and interrupt modes
- Flexibility for adding other features
- The C_UART was developed in VHDL
- Synthesizes to approximately 650 gates depending on the process used
Symbol
Pin Description
Name |
Type |
Polarity |
Description |
CLK |
In |
Rising |
System Clock |
XRST |
In |
Low |
Master Reset |
XUWR |
In |
Rising |
Decoded UART Write Control for Transmitter Register |
UARTRS |
In |
- |
Register Select (0 = Status; 1 = RX_Register) |
URD |
In |
Falling |
Decoded UART Read |
DIN [7:0] |
In |
- |
Input Data Bus |
DOUT [7:0] |
Out |
- |
Output Data Bus |
CLK16 |
In |
Rising |
Transmitter/Receiver Master Clock |
TxDATA |
Out |
- |
Transmitter Data |
TxREADY |
Out |
Low |
Transmitter Empty (ready to accept new character) |
RxDATA |
In |
- |
Receiver Data |
RxREADY |
Out |
Low |
Receiver Ready (character ready to be transferred to CPU) |
Block Diagram

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