Programmable Communication Interface

Function Description

The C8251 programmable communications interface (USART) core provides data formatting and control to a serial communication channel.

The core has select, read/write, interrupt and bus interface logic features that allow data transfers over an 8-bit bi-directional parallel data bus system. With proper formatting and error checking, the core can transmit and receive serial data, supporting both synchronous and asynchronous operation.


  • Synchronous and asynchronous operation
  • Programmable data word length, parity and stop bits
  • Parity, overrun and framing error checking instructions and counting loop interactions
  • Supports up to 1.750 Mbps transmission rates
  • Divide-by 1,-16,-64 mode
  • False start bit deletion
  • Automatic break detection
  • Internal and external synch character detection
  • Peripheral modem control functions
  • The C8251 was developed in VHDL and synthesizes to approximately 2,300 gates depending on the technology used
  • Functionality based on the Intel 8251A device



C8251 - Symbol


Pin Description

Name Type Polarity Description
RESET In Low External Rest
CLK In - Master Clock
TX_CLK In - Transmit Clock
RX_CLK In - Receive Clock
RDn In Low Read Control
WRn In Low Write Control
CSn In Low Chip Select
C_Dn In - Control/Data Select
EXTSYNDET In High External Synch Detect
DIN[7:0] In - Data Input Bus
CTSn In Low Clear-to-Send
DSRn In Low Data Set Ready
RxD In - Receive Data
D0[7:0] Out - Data Output Bus
TxD Out - Transmit Data
TxE Out Low Transmitter Empty
RTSn Out Low Request-to-Send
DTRn Out Low Data Terminal Ready
TxRDY Out High Transmit Ready
RxRDY Out High Receiver Ready
SYN_BREAK Out Low Sync/Break Detect


Block Diagram

C8251 - Block


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