Universal Asynchronous Receiver/Transmitter

Function Description

The C8250 programmable asynchronous communications interface (UART) core provides data formatting and control to a serial communication channel.

The core has select, read/write, interrupt and bus interface logic features that allow data transfers over an 8-bit bi-directional parallel data bus system. With proper formatting and error checking, the core can transmit and receive serial data, supporting asynchronous operation.


  • Full double buffering
  • Asynchronous operation
  • Independently controlled Transmit, Line Status, Receive, and Data Set Interrupts
  • Programmable data word length (5 - 8 bit), parity and stop bits
  • Parity, overrun and framing error checking
  • Supports up to 1.5 Mbps transmission rates
  • Programmable Baud Rate Generator allows division of any reference clock by 1 to (216-1) and generates an internal 16 X Clock
  • False start bit detection
  • Automatic break generation and detection
  • Internal diagnostic capabilities
  • Peripheral modem control functions
  • The C8250 was developed in VHDL and synthesizes to approximately 2,000 gates depending on the process used



C8250 - Symbol


Pin Description

Name Type Polarity Description
RESET In High External Rest
CLK In - Master Clock
RCLK In - Receive Clock
ADSn In Low Address Strobe
RDn In Low Read Control
WRn In Low Write Control
CS0 In High Chip Select 0
CS1 In High Chip Select 1
CS2n In Low Chip Select2
DIN[7:0] In - Data Input Bus
CTSn In Low Clear-to-Send
DSRn In Low Data Set Ready
DCDn In Low Data Carrier Detect
RXDATA In - Receive Data
RIn In Low Ring Indicator
A[2:0] In - Register Select
D0[7:0] Out - Data Output Bus
TXDATA Out - Transmit Data
DDIS Out High Driver Disable
RTSn Out Low Request-to-Send
DTRn Out Low Data Terminal Ready
OUT1n Out Low Output 1
OUT1n Out Low Output 2
CSOUT Out High Chip Select Out
INTRPT Out High Interrupt
BOUDOUTn Out Low Baud Out


Block Diagram

C8250 - Block


Gate-level Licenses

  • Post-synthesis gate-level netlist
  • Testbench
  • Vectors for testing the functionality of the core
  • Expected results for testbench

VHDL Source Licenses

  • VHDL RTL source code
  • Testbench
  • Example testbench wrapper for post-route simulation
  • Vectors for testbench
  • Simulation script
  • Synthesis script
  • Expected results for testbench

Core Modifications

The C8250 core can be customized to include different CPU interface. Please contact Moxsyn for any required modifications.

| Home | Search | Products |Support | SalesContact Moxsyn |

Please send your comments to webmaster@moxsyn.com