C6850
Asynchronous Communications Interface
Synthesizable Core

Function Description

The C6850 asynchronous communications interface (ACIA) core provides data formatting and control to the asynchronous data communications of data bus systems.

The core has select, enable, read/write, interrupt and bus interface logic features that allow data transfers over an 8-bit bi-directional parallel data bus system. With proper formatting and error checking, the core can transmit and receive serial data.

In addition, a programmable control register provides the core with a transmit control, a receive control, an interrupt control, variable word lengths and clock division ratios. Three control lines are provided for peripheral or modem operation.

Features

  • Programmable data word length, parity and stop bits
  • Parity, overrun and framing error checking instructions and counting loop interactions
  • Supports transmission rates over the 1.0 Mbps spec
  • False start bit deletion
  • Peripheral modem control functions
  • The C6850 was developed in VHDL and synthesizes to approximately 1,300 gates depending on the process used
  • Functionality based on the Motorola MC6850

 

Symbol

C6850 - Symbol

 

Pin Description

Name Type Polarity Description
EXT_RST In High External Reset
TX_CLK In - Transmit Clock
RX_CLK In - Receive Clock
RXW In - Read/Write
CSn In Low Chip Select
RS In Low Register Select
E In - Enable (clock)
DIN [7:0] In Low Data Input Bus
RXDATA In - Receive Data
CTSn In Low Clear - to - Send
DCDn In Low Data Carrier Direct
IRQn Out Low Interrupt Request
TXDATA Out - Transmit Data
RTSn Out Low Request - to - Send
DO [7:0] Out Low Data Output Bus

 

 

 

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